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<h2><img class="alignright wp-image-4713 size-medium" src="https://ipintelligencereport.bakerhostetlerblogs.com/wp-content/uploads/sites/11/2017/06/software-international-binary-code-iStock_5664283_LARGE-300x194.jpg" alt="" width="300" height="194" />Introduction</h2>
In Visual Memory v. NVIDIA (<a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__p.feedblitz.com_t3.asp-3F_36137_1027711_5728343-5F_www.cafc.uscourts.gov_sites_default_files_opinions-2Dorders_16-2D2254.Opinion.8-2D11-2D2017.1.PDF&amp;d=DwMGaQ&amp;c=tlFs99Fl3Rlo51LXUBQcug&amp;r=AJpkHl5lJQbOir3s_QGWOhYtX-YEaYz05eOHsG1wkdY&amp;m=LPGHpyo5yV6k5j_r_H8VWYWjp76EhzfuP8T0a27l66w&amp;s=b5oBoeCPMKSR9gnQd9MXwJZgQr746ArKcQfU-IqJefI&amp;e=">Fed. Cir. 2017</a>), the Federal Circuit reversed the district court’s holding that Visual Memory’s U.S. Patent No. 5,953,740 is drawn to patent-ineligible subject matter. Instead, the court ruled that the ’740 patent claims an improvement to computer memory systems and is not directed to an abstract idea.
<h2>The ’740 Patent</h2>
At a high level, the ’740 patent describes a computer memory system that can be connected to different kinds of processors. The memory system has “programmable operational characteristics” based on characteristics of the processor; it includes several caches and a main memory (DRAM) connected to a bus. One cache can be programmed to store only code data, and another cache can be programmed to buffer data writes to the main memory only from the processor. The main memory can be programmed to selectively reopen either code or non-code data pages. (See ’740 patent abstract.) Figure 1 of the patent is copied below.

<img class="aligncenter size-full wp-image-4751" src="https://ipintelligencereport.bakerhostetlerblogs.com/wp-content/uploads/sites/11/2017/08/IP1.png" alt="" width="640" height="429" />

As shown in Figure 1, the memory system 10 includes a system memory (DRAM) 12, an internal cache 16, a pre-fetch cache 18 and a write buffer cache 20, each connected to bus 14. Access to DRAM 12 is controlled by DRAM controller 22. The data stored in system memory 12 can be divided into code data (instructions) and non-code data. The memory system 10 is designed for use with a host processor in combination with other bus masters or devices that compete with the host processor for access to the memory system 10. (See ’740 patent col. 3 lines 34-50.)

There are several aspects of the written description worth noting:
<ol>
 	<li>The ’740 patent discloses an important feature of the invention: the functionality of the various caches may be varied depending upon the host processor type (e.g., 386, 386sx or 486). The memory system 10 has “programmable operational characteristics based on characteristics of the processor.” For example, according to the patent, the internal cache 16 holds data selected solely on the basis of memory accesses by the host processor. Thus, the internal cache 16 is dedicated to the host processor and will not be affected by memory accesses by other bus masters. Another feature of the caches is that the pre-fetch cache 18 contains solely code data pre-fetched from the DRAM 12. Furthermore, it pre-fetches only code based on a memory access by the host processor. The write buffer cache 20 buffers only data to be written into the DRAM 12. (See ’740 patent col. 3 line 51-col. 4 line 20.)</li>
 	<li>The patent also discloses that another important feature of the invention is the separation of the functionality of each of the caches and the selective definition of those functions based on the processor type. According to the patent, the system is able to achieve or exceed the performance of a system utilizing a cache many times larger than the cumulative size of the subject caches. (See ’740 patent col. 4 lines 21-45.)</li>
 	<li>In addition, the patent asserts that a significant advantage of the dual- or multiple-mode operation of the invention is that it allows different types of processors to be installed with the memory system 10 without significantly compromising their individual performance. (Id.)</li>
 	<li>In addition, the patent includes a microfiche appendix with 263 frames of CDL listing. According to the patent, CDL is “a high level hardware description language” that “unambiguously defines the hardware for a digital logic system.” (See ’740 patent col. 6 lines 2-12.) “The CDL listing completely defines a preferred embodiment of a computer memory system 10. The listing may be compiled to generate a ‘C’ source code which may then be compiled by a C compiler to generate a standardized C Object File Format (COFF). The COFF is then input to a logic synthesis program to provide a detailed logic schematic.” (Id.)</li>
</ol>
Claim 1 appears to be quite broad. The only (potentially) unconventional feature is the functional limitation “wherein a programmable operational characteristic of said system determines a type of data stored by said cache.”
<ol>
 	<li>A computer memory system connectable to a processor and having one or more programmable operational characteristics, said characteristics being defined through configuration by said computer based on the type of said processor, wherein said system is connectable to said processor by a bus, said system comprising:</li>
</ol>
 - a main memory connected to said bus; and
 - a cache connected to said bus,
wherein a programmable operational characteristic of said system determines a type of data stored by said cache.
(Claim 1 of ’740 patent, emphasis supplied.)
<h2>Patent Eligibility Under 35 U.S.C. § 101</h2>
Visual Memory sued NVIDIA for infringement of the ’740 patent. In response, NVIDIA filed a motion to dismiss for failure to state a claim pursuant to Federal Rule of Civil Procedure 12(b)(6). The district court granted NVIDIA’s motion. Under step 1 of the Alice test,[1] the court concluded that the claims were directed to the “abstract idea of categorical data storage,” which humans have practiced for many years. Visual Memory LLC v. NVIDIA Corp., No. 15-789, 2016 WL 3041847, at *4 (D. Del. May 27, 2016). The court’s step 2 analysis found no inventive concept because the claimed computer components – a main memory, cache, bus and processor – were generic and conventional. The ’740 patent’s programmable operational characteristics did not provide the inventive concept, according to the district court, because they represent generic concepts that determine the type of data to be stored by the cache, and the patent fails to explain the mechanism for accomplishing the result. (Id. at *7.)
<h3>Alice Step 1</h3>
The Federal Circuit begins its analysis with Alice step 1, i.e., determining whether the claims are directed to an abstract idea. The court notes that the “Supreme Court’s formulation makes clear that the first-stage filter is a meaningful one, sometimes ending the § 101 inquiry.” (Opinion at 7.) “In this regard, we must articulate with specificity what the claims are directed to . . . and ask whether the claims are directed to an improvement to computer functionality versus being directed to an abstract idea.” (Id.)
<h4>Guideposts</h4>
Next, the court discusses two recent cases, Enfish and Thales, that inform its evaluation of whether the claims are “directed to” an abstract idea:
<ol>
 	<li>In Enfish, the court held that claims reciting a self-referential table for a computer database were patent-eligible under Alice step 1 because the claims were directed to an improvement in the computer’s functionality. In this respect, the court referenced its explanation that the plain focus of the claims is on an improvement to computer functionality itself, not on economic or other tasks for which a computer is used in its ordinary capacity. In addition, the court noted that, in Enfish, the specification described the benefits of using a self-referential table – faster searching and more effective data storage – and highlighted the differences between the claimed self-referential table and a conventional database structure. Based on this, the court in Enfish rejected the district court’s characterization of the claims as being directed to the abstract idea of “storing, organizing, and retrieving memory in a logical table.” (Opinion at 8.)<a href="#_ftn2" name="_ftnref2">[2]</a></li>
 	<li>In Thales, the court determined that claims reciting a unique configuration of inertial sensors, and the use of a mathematical equation for calculating the location and orientation of an object relative to a moving platform, were patent-eligible under Alice step 1. In Thales, the patented system achieved greater accuracy than prior art systems by measuring inertial changes of a tracked object relative to a moving platform’s reference frame. The court overruled the lower court’s conclusion that the claims were directed to the abstract idea of using mathematical equations to determine the position of a moving object relative to a moving reference frame. Instead, the court concluded that the claims were directed to systems and methods that use inertial sensors in a nonconventional manner to reduce errors in measuring the relative position and orientation of a moving object on a moving reference frame. (Opinion at 8-9.)<a href="#_ftn3" name="_ftnref3">[3]</a></li>
</ol>
<h4>Claims</h4>
With these guideposts in mind, the court reviewed claim 1 of the ’740 patent as well as dependent claims 2, 3, 6 and 7. The court noted that claim 1 requires a memory system “having one or more programmable operational characteristics, said characteristics being defined through configuration by said computer based on the type of said processor” (recited in the preamble of claim 1) and “determin[ing] a type of data stored by said cache” (recited in the wherein clause noted above). (Opinion at 9.) In addition, the court noted that dependent claims 2 and 3 narrow the cache’s programmable operational characteristic to storing certain types of data (“only code data or . . . both code data and non-code data”) and buffering data from certain sources (“buffering of data solely from said bus master or . . . both from said bus master and [from] said processor”), respectively. (Id.) The court further noted that claim 6 recites the fast page mode embodiment with a programmable operational characteristic, and dependent claim 7 defines the programmable operational characteristic as the type of data to be stored. (Id.) As the court noted, “None of the claims recite all types and all forms of categorical data storage.” (Id., emphasis supplied.)
<h4>Written Description</h4>
Turning to the written description, the court noted that the specification explains that multiple benefits flow from the ’740 patent’s improved memory system. The court noted the specification’s disclosure that a memory system with programmable operational characteristics defined by the processor connected to the memory system permits “different types of processors to be installed with the subject memory system without significantly compromising their individual performance.” In this respect, the court noted that the patent’s teachings both obviate the need to design a separate memory system for each type of processor, which proved to be costly and inefficient, and at the same time avoid the performance problems of prior art memory systems. The court further noted that, in addition to enabling interoperability with multiple different processors, the selective definition of the functions of the cache memory based on processor type results in a memory system that can outperform a prior art memory system armed with a cache many times larger than the cumulative size of the subject caches. (Opinion at 9-10.)

The court then compared the invention with Enfish’s self-referential table and the motion-tracking system in Thales:
[T]he claims here are directed to a technological improvement: an enhanced computer memory system. The ’740 patent’s claims focus on a “specific asserted improvement in computer capabilities” – the use of programmable operational characteristics that are configurable based on the type of processor – instead of “on a process that qualifies as an ‘abstract idea’ for which computers are invoked merely as a tool.” Enfish, 822 F.3d at 1336. And like the patents at issue in Enfish and Thales, the specification discusses the advantages offered by the technological improvement. Accordingly, this is not a case where the claims merely recite the “use of an abstract mathematical formula on any general purpose computer,” “a purely conventional computer implementation of a mathematical formula” or “generalized steps to be performed on a computer using conventional computer activity.” Id. at 1338 (collecting cases where claims were directed to patent-ineligible subject matter).
(Opinion at 10-11, emphasis supplied.) The court goes on to distinguish cases such as Content Extraction &amp; Transmission LLC, 776 F.3d 1343 (Fed. Cir. 2014) and In re TLI Communications LLC Patent Litigation, 823 F.3d 607 (Fed. Cir. 2016), where the inventions were found not to provide a specific improvement to computer functionality. (Id.) In sum, the fact that the written description included specific disclosures concerning improvements in the functioning of the computer was deemed to be key to a finding that the claims were not “directed to” an abstract idea.
<h3>Alice Step 2</h3>
Because the court concluded that the claims of the ’740 patent are not directed to an abstract idea, it did not proceed to step 2 of the Alice test.
<h2>Conclusion</h2>
An important lesson to be drawn from this case is that a robust written description, one including technical detail and specific statements concerning how the disclosed invention improves upon the prior art, can be key to showing that the claims are not directed to an abstract idea and thus are patent-eligible under § 101. Even broader claims – such as claim 1 of the ’740 patent – that do not recite the technical detail and improvements can be saved by a robust written description.

<hr />

[1] Alice Corp. v. CLS Bank International, 134 S. Ct. 2347 (2014).

[2] We reviewed Enfish last year in our article <a href="https://www.ipintelligencereport.com/2016/05/12/major-101-decision-enfish-v-microsoft/">Major 101 Decision – Enfish v. Microsoft</a>. In that article, we noted the court’s statement that claims directed to software, as opposed to hardware, are not inherently abstract and can be analyzed at the first step of the Alice analysis; in other words, software can make nonabstract improvements to computer technology just as hardware improvements can.

[3] My partner Allen Sokal reviewed the Thales decision in <a href="https://www.ipintelligencereport.com/2017/03/13/federal-circuit-appears-to-narrow-the-exceptions-to-35-u-s-c-%c2%a7-101/">Federal Circuit Appears to Narrow the Exceptions to 35 U.S.C. § 101</a>. Here it was noted that the lesson for patent owners was to describe the claimed invention as an unconventional approach that produces significantly improved results.

Visual Memory v. NVIDIA: The Importance of a Robust Written Description